Deliverables

4	GDSII and LVS Spice netlist, behavioral, synthesis, and 
LEF models, and extensive user documentation.

4	Integration support to ensure 
a successful tape out (included 
in standard design license fee).

Deskew PLL

Features

4	Designed to eliminate 
clock distribution latency in systems and individual chips.

4	Precisely aligns the clock distribution output with a 
reference clock.

4	Provides a zero-delay feedback divider and zero-skew divided clock outputs.

Specifications
Part No. TCI-TN16FFPLL-DSLPLL

- Divided reference frequency range	7.81MHz - 1GHz
- Total output frequency range	200MHz - 1GHz
- /1 output frequency range	200MHz - 1GHz
- Reference divider values	1-64
- Feedback divider values	1-64
- Divided outputs provided	/1, /2, /4
- /1 output multiples of div. reference	1-64
- Bandwidth adjustment div. range	1-4096
- Feedback signal delay (max)	NDA Required
- Output duty cycle (nom, tol)	50%, +/-2%
- /1, /2, /4 rising phase error (max)	NDA Required
- Static phase error (max)	NDA Required
- Period jitter (P-P) (max)	NDA Required
- Input-to-output jitter (P-P) (max)	NDA Required

- Power dissipation (nom)	NDA Required
- Reset pulse width (min)	5µs
- Reset /1 output frequency range	5MHz - 50MHz
- Lock time (min allowed)	NDA Required
- /1 freq. overshoot (full-~/half-~) (max)	NDA Required
- Area (including isolation) (max)	NDA Required

- Number of PLL supply pkg. pins	1 VDDA, 1 VSSA (preferred)
- Low freq. supply noise est. (P-P) (max)	+/-5% VDDA
- Low freq. sub. noise est. (P-P) (max)	+/-5% VDDA
- Reference input jitter (long-term, P-P) (max)	NDA Required
- Reference/Feedback H/L pulse width (min)	NDA Required

- Process technology	TSMC CLN16FF+LL 16nm
- Supply voltage (VDD, VDDA) (nom, tol)	0.8V, +/-10%
- Junction temperature (nom, min, max)	70C, -40C, 125C
*	Jitter numbers are worst-case estimates with 10% VDDA supply and 
substrate noise—actual results will be better.