Deliverables

4	GDSII and LVS Spice netlist, behavioral, synthesis, and 
LEF models, and extensive user documentation.

4	Integration support to ensure 
a successful tape out (included 
in standard design license fee).

Clock Generator PLL

Features

4	Designed as a very flexible clock multiplier capable of multiplying an input clock 
from 1 to 4096 with very 
small period jitter while operating at the highest possible bandwidth.

4	Delivers optimal jitter performance over all multiplication settings.

4	Supports fractional-N frequency multiplication.

4	Available with multi-phase outputs and with an I/O voltage regulator.

4	Ideal for system clock generation, SerDes and 
video clock applications.

Specifications
Part No. TCI-TN20SOC-CGHPLL

- Divided reference frequency range	427KHz - 3.5GHz
- Total output frequency range	43.8MHz - 3.5GHz
- /1 output frequency range	700MHz - 3.5GHz
- Reference divider values	1-64
- Feedback divider values	1-4096
- Output divider values	1, 2-16 (even only)
- /1 output multiples of div. reference	1-4096
- Bandwidth adjustment div. range	1-4096
- Feedback signal delay (max)	n/a (FB internal)
- Output duty cycle (nom, tol)	50%, +/-5% (/1), +/-2% (/N)
- Static phase error (max)	n/a
- Period jitter (P-P) (max)	NDA Required
- Input-to-output jitter (P-P) (max)	NDA Required

- Power dissipation (nom)	NDA Required
- Reset pulse width (min)	5µs
- Reset /1 output frequency range	20MHz - 200MHz
- Lock time (min allowed)	NDA Required
- /1 freq. overshoot (full-~/half-~) (max)	NDA Required
- Area (including isolation) (max)	NDA Required

- Number of PLL supply pkg. pins	1 VDDA, 1 VSSA (preferred)
- Low freq. supply noise est. (P-P) (max)	+/-5% VDDA
- Low freq. sub. noise est. (P-P) (max)	+/-5% VDDA
- Reference input jitter (long-term, P-P) (max)	NDA Required
- Reference H/L pulse width (min)	NDA Required

- Process technology	TSMC CLN20SOC 20nm
- Supply voltage (VDD, VDDA) (nom, tol)	0.9V, +/-10%
- Junction temperature (nom, min, max)	70C, -40C, 125C
*	Jitter numbers are worst-case estimates with 10% VDDA supply and 
substrate noise—actual results will be better.