Deliverables

4	GDSII and LVS Spice netlist, behavioral, synthesis, and 
LEF models, and extensive user documentation.

4	Integration support to ensure 
a successful tape out (included 
in standard design license fee).

DDR DLL

Features

4	Designed for high-speed DDR style interface applications.

4	Generates precise delays that can be programmed from 0 to 360 degrees of the reference period.

4	Delays multiple periodic or aperiodic signals independent of voltage and temperature.

4	Delivers optimal jitter 
performance over a wide 
frequency range.

4	Available in flexible form factors for easier integration.

Specifications
Part No. TCI-TN28HPL-DDRXHDLL

- Reference frequency range (MADJ=76)	246MHz - 1.23GHz
- Total reference frequency range 	73.3MHz - 1.23GHz
- Slave delay adjustment range	0% - 50% of reference cycle
- Slave delay adjustment resolution	1.3% of reference cycle
- Specified master adjustment setting (MADJ)	76
- Allowed master adjustment range (MADJ)	76 - 255
- Specified slave adjustment range (ADJ)	0 - 38
- Slave delay equation	ADJ[7:0]/MADJ[7:0]*Tref
- Number of slaves in cluster	2
- Slave delay DNL (max)	NDA Required
- Slave delay INL (max)	NDA Required
- Slave delay jitter (P-P) (max)	NDA Required
- Total slave timing uncertainty (max)	NDA Required

- Power dissipation (nom)	NDA Required
- Reset pulse width (min)	1µs
- Lock time (min allowed)	NDA Required
- Area (master + 2 slaves, isolation) (max)	NDA Required

- Added core supply package pins	1 VDD and 1 VSS
- Low freq. supply noise est. (P-P) (max)	+/-5% VDD
- Low freq. sub. noise est. (P-P) (max)	+/-5% VDD
- Reference input jitter (period, P-P) (max)	NDA Required
- Reference input duty-cycle range	NDA Required
- High/low slave input pulse width (min)	NDA Required
- Slave inputs need not be periodic
- Reference input 10%-90% edge time (max)	150ps
- Slave input 10%-90% edge time (max)	150ps
- Slave output loading (max)	200fF

- Process technology	TSMC CLN28HPL 28nm
- Supply voltage (nom, tol)	1.0V, +/-10%
- Junction temperature (nom, min, max)	70C, -40C, 125C
*	Jitter numbers are worst-case estimates with 10% VDD supply and 
substrate noise—actual results will be better.