Deliverables

4	GDSII and LVS Spice netlist, behavioral, synthesis, and 
LEF models, and extensive user documentation.

4	Integration support to ensure 
a successful tape out (included 
in standard design license fee).

Spread Spectrum PLL

Features

4	Designed for PC, networking, and consumer-electronics applications where spread-spectrum clock sources are required to satisfy FCC requirements for peak RF spectral emissions.

4	Spreading rate and spreading depth are precisely adjustable to allow the designer to dial-in the desired characteristics.

4	14-bit fractional-N feedback divider with 3 bits of precise control.

4	Available with multi-phase outputs.

Specifications
Part No. TCI-TN55LP-SSHPLL

- Divided reference frequency range	147KHz - 600MHz
- Total output frequency range	15MHz - 1.2GHz
- /1 output frequency range	240MHz - 1.2GHz
- Reference divider values	1-64
- Integer feedback divider values	2-4095
- Fractional feedback divider bits	14
- Output divider values	1, 2-16 (even only)
- /1 output multiples of div. reference	2-4095
- Bandwidth adjustment div. range	1-4096
- Spreading depth adjustment range (typ)	0% - -10%
- Spreading rate adjustment range (typ)	15KHz - 4MHz
- Feedback signal delay (max)	n/a (FB internal)
- Output duty cycle (nom, tol)	50%, +/-5% (/1), +/-2% (/N)
- Static phase error (max)	n/a
- Period jitter (P-P) (max)	NDA Required
- Input-to-output jitter (P-P) (max)	NDA Required

- Power dissipation (nom)	NDA Required
- Reset pulse width (min)	5µs
- Reset /1 output frequency range	120MHz - 600MHz
- Lock time (min allowed)	NDA Required
- /1 freq. overshoot (full-~/half-~) (max)	NDA Required
- Area (including isolation) (max)	NDA Required

- Number of PLL supply pkg. pins	1 VDDA, 1 VSSA (preferred)
- Low freq. supply noise est. (P-P) (max)	10% VDDA
- Low freq. sub. noise est. (P-P) (max)	10% VDDA
- Reference input jitter (long-term, P-P) (max)	NDA Required
- Reference H/L pulse width (min)	NDA Required

- Process technology	TSMC CLN55LP 55nm
- Supply voltage (VDD, VDDA) (nom, tol)	1.2V, +/-10%
- Junction temperature (nom, min, max)	70C, -40C, 125C
*	Jitter numbers are worst-case estimates with 10% VDDA supply and 
substrate noise—actual results will be better.