Deliverables

4	GDSII and LVS Spice netlist, behavioral, synthesis, and 
LEF models, and extensive user documentation.

4	Integration support to ensure 
a successful tape out (included 
in standard design license fee).

General Purpose PLL

Features

4	Designed as a wide range 
clock multiplier with deskew 
capability.

4	Delivers optimal jitter 
performance over all 
multiplication settings.

4	Low area and low power.

4	Suitable for system clock, 
DDR and general  purpose 
applications.

4	Ideal for cost sensitive 
applications.

Specifications
Part No. TCI-UL65SP-GPMPLL

- Divided reference frequency range	10.2MHz - 1.3GHz
- Total output frequency range	16.2MHz - 1.3GHz
- /1 output frequency range	260MHz - 1.3GHz
- Reference divider values	1-16
- Feedback divider values	1-64
- Output divider values	1-16
- /1 output multiples of div. reference	1-64
- Bandwidth adjustment div. range	1-64
- Feedback signal delay (max)	NDA Required
- Output duty cycle (nom, tol)	50%, +/-2%
- Static phase error (max)	NDA Required
- Period jitter (P-P) (max)	NDA Required
- Input-to-output jitter (P-P) (max)	NDA Required

- Power dissipation (nom)	NDA Required
- Reset pulse width (min)	5µs
- Reset /1 output frequency range	130MHz - 650MHz
- Lock time (min allowed)	NDA Required
- /1 freq. overshoot (full-~/half-~) (max)	NDA Required
- Area (including isolation) (max)	NDA Required

- Number of PLL supply pkg. pins	1 VDDA, 1 VSSA (preferred)
- Low freq. supply noise est. (P-P) (max)	10% VDDA
- Low freq. sub. noise est. (P-P) (max)	10% VDDA
- Reference input jitter (long-term, P-P) (max)	NDA Required
- Reference/Feedback H/L pulse width (min)	NDA Required

- Process technology	UMC L65SP 65nm
- Supply voltage (VDD, VDDA) (nom, tol)	1.0V, +/-10%
- Junction temperature (nom, min, max)	70C, -40C, 125C
*	Jitter numbers are worst-case estimates with 10% VDDA supply and 
substrate noise—actual results will be better.