"We selected TCI's clock generator PLL because of its small size, wide frequency range and superior low-jitter performance. This will enable our ASIC customers to successfully implement multiple SPI-4.2 macros in their high-end telecommunication ASICs and help meet the tight jitter and power budgets required for 10 Gbps SONET/SDH systems."

Hideya Horikawa
Senior Design Engineering Manager
Renesas



It is not in our business interest to release the proprietary aspects of our PLL designs. Our design kits do not include any internal schematics and our licensing agreement does not permit reverse engineering of our PLL designs.


20-24 Jul 20 Design Automation Conference
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24 Aug 20 TSMC NA Technology Symposium
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25 Aug 20 TSMC NA OIP Ecosystem Forum
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25 Aug 20 TSMC Europe Technology Symposium
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