"We selected TCI's clock generator PLL because of its small size, wide frequency range and superior low-jitter performance. This will enable our ASIC customers to successfully implement multiple SPI-4.2 macros in their high-end telecommunication ASICs and help meet the tight jitter and power budgets required for 10 Gbps SONET/SDH systems."

Hideya Horikawa
Senior Design Engineering Manager

We provide all of the following for each of our PLLs:

  • Complete specifications
  • User guidelines
  • Behavioral simulation model
  • Complete layout (GDSII)
  • Layout vs. schematic netlist
  • ...

24 Apr 24 TSMC NA Technology Symposium
Santa Clara, California

28 May 24 TSMC China Technology Symposium
Shanghai, China

24-26 Jun 24 Design Automation Conference
San Francisco, California

25 Sep 24 TSMC NA OIP Ecosystem Forum
Santa Clara, California

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