True Circuits Attends 60th Design Automation Conference and Celebrates 25 Years of Timing Excellence!
True Circuits Announces Availability of JSPICETM Simulation and Design Environment
True Circuits Attends 59th Design Automation Conference
True Circuits Introduces New Synthesizable Precision PLL and Synthesizable Micro PLLs and DLLs and Demonstrates Silicon Proven DDR PHY
True Circuits Participates in First Virtual DAC! Showcases Silicon Proven PLLs, DLLs and DDR 4/3 PHYs
True Circuits Demonstrates Silicon Proven DDR 4/3 PHY at DAC
Response to DeepChip.com article on the demise of analog PLLs, by John Maneatis
True Circuits Attends Design Automation Conference
True Circuits Provides Low Power PLL Technology to SiFlower in China
True Circuits Signs Multi-year PLL License with Canaan Creative in China
True Circuits Signs Five Year PLL License with Tsinghua University in China
True Circuits Attends the TSMC 2017 China OIP Ecosystem Forum
True Circuits Attends the TSMC 2017 NA OIP Ecosystem Forum
True Circuits Showcases State-of-the-art PLLs and 16nm IP
True Circuits Announces New Line of IoT PLLs (Datasheet)
True Circuits Announces New Line of PLLs, The Ultra PLL (Datasheet)
True Circuits Showcases Revolutionary New DDR 4/3 PHY at Design Automation Conference
See Our Ad in the Fall Issue of Chip Design Magazine
True Circuits Introduces Revolutionary New DDR 4/3 PHY at Design Automation Conference
See Our Ad in the Winter Issue of Chip Design Magazine
True Circuits 28nm PLL and DLL Hard Macros Featured at TSMC Technology Symposiums in San Jose, Austin and Shanghai
True Circuits PLLs used by ARM in Verification of Cortex-A9 Microprocessor Cores
True Circuits Announces New Line of Multi Phase DLLs
True Circuits Announces New Line of General Purpose PLLs
See Our Ad in the GTC2010 Program
See Our Product Showcase in the Jun-Jul Issue of Chip Design
True Circuits 40nm PLL and DLL Hard Macros Featured at TSMC Technology Symposium in San Jose
ChipEstimate.com Announces New IP Partners
See Our Product Showcase in the Jan-Feb Issue of Chip Design
True Circuits Analog PLL & DLL Hard Macros Featured at GSA Suppliers Expo
True Circuits' John Maneatis Speaks at GSA IP Conference Panel
True Circuits' Analog PLL & DLL Hard Macros Featured at the Second Common Platform Technology Forum
True Circuits PLL and DLL Hard Macros Featured at TSMC Technology Symposium in San Jose
See Our Ad in the June/July Issue of Chip Design
True Circuits' Analog PLL & DLL Hard Macros Featured at the First Common Platform Technology Forum
True Circuits Analog PLL & DLL Hard Macros Featured at FSA Suppliers Expo
See Our Article "Phase-Locked Loops Demystified" in the August 28 Issue of Chip Estimate's IP Connections Newsletter
See Our Ad in the July 19 Issue of Electronic Design
True Circuits PLL and DLL Hard Macros Featured at TSMC Technology Symposium
True Circuits Announces New Line of 65nm Timing IP
True Circuits Features New Line of 65nm PLL & DLL Intellectual Property
eSilicon offers complete 90nm DDR2 Memory Interface Solutions
True Circuits PLL and DLL Hard Macros Featured at TSMC Technology Symposiums
True Circuits PLLs Selected by Icera
True Circuits Moves to Larger Headquarters
See Our Ads in 2005 Issues of Chip Design Magazine
True Circuits Introduces New Line of High Resolution Clock Generator PLLs
True Circuits Analog PLL & DLL Hard Macros Featured at Chartered Technology Forum 2005
True Circuits' John Maneatis to Speak at Semico's Semiconductor Intellectual Property Conference (Slides)
True Circuits PLL and DLL Hard Macros Featured at TSMC Technology Symposiums in San Jose and Boston
True Circuits Selects Amos Technologies to Distribute Its Silicon-Proven Timing Intellectual Property
TriCN Signs Reseller Agreement with True Circuits for Silicon-Proven Timing IP
True Circuits Invites ASIC, FPGA & SoC Designers to the ARM Developers' Conference to Learn More About Using Hard Timing Macros in ARM Cores
FSA's October 7th Semiconductor IP Workshop Features Presentation by True Circuits on Selecting and Implementing PLLs (Paper)
See Our Ad in the July 19 Issue of EE Times
True Circuits Introduces New Line of Phase-Locked Loop Hard Macros
Leopard Logic Selects True Circuits IP for Gladiator CLD Configurable Logic Devices
True Circuits Selects The LogicWorks to Distribute Its Silicon-Proven Timing Intellectual Property
True Circuits Analog IP Ships in Ubicom's Wireless Network Processor
True Circuits PLLs are Recognized with a Wireless Systems Design 2004 Industry Award
True Circuits PLL Critical to Parama Networks' new ADM-on-a-Chip
See Article by Ron Wilson on Our New DDR DLLs in the Semiconductors Section of the October 27 Issue of EE Times Magazine
True Circuits Announces NEC Electronics Corporation Has Implemented a Low-jitter PLL in their SPI-4.2 Interface Hard Macro
True Circuits Introduces Delay-Locked Loop Hard Macros
See Our Feature Article "Selecting PLLs for ASIC Applications Requires Tradeoffs" in the September Issue of Planet Analog Magazine
True Circuits Exhibits for the First Time at the FSA Suppliers Expo
See Our Ad in the August 18 Issue of EE Times
See Our Feature Article "PLLs Plot An Adjustable Course" in the June Issue of Wireless System Design Magazine (Article)
True Circuits Introduces Spread Spectrum and Low Bandwidth Phase-Locked Loop Hard Macros
See Our Ad in the March 31 Issue of EE Times
Technical Paper Co-authored by TCI and TI Employees Accepted for Presentation at ISSCC 2003 (Slides)
True Circuits Analog IP Enables Oak Technology to Expedite HDTV Circuit Design
Stephen Maneatis discusses TCI's business strategy in the 50th Anniversary Issue of Electronic Design Magazine
True Circuits Joins Design & Reuse Web Portal for IP and SoC Exchange
John Maneatis' Feature Article Republished in EE Times-Asia (Complete Original Version)
See Our Ad in the June 10 Issue of EE Times
True Circuits Reports Success from Seventh World® Ad Campaign, Begins Public Relations Program
See Our Ad in the January Issue of ISD Magazine
John Maneatis Authors Feature Article in the January Issue of ISD Magazine (Complete Original Version)
True Circuits, Inc. Announces New Family of Phase-Locked Loops
True Circuits' Phase-Locked Loops Used by ARM in Verification of Microprocessor Cores
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