Shenzhen, China, November 7, 2017 -- True Circuits, Inc. (TCI), a leading
provider of analog and mixed-signal intellectual property (IP) for the
semiconductor, systems and electronics industries announced today it has
signed a five year license with China's prestigious Tsinghua University in
Beijing which enables students to employ high-quality, low-jitter
Phase-Locked Loop (PLL) IP in semiconductor chips used for research and
development. The license allows Tsinghua University to use PLLs in multiple
TSMC foundry processes and enables students to develop a wide variety of
chips in high-performance applications. The license builds on prior
collaboration between TCI and Tsinghua University and is part of a growing
effort by both parties to support advanced curriculum and real world
learning for future semiconductor engineers in China.
"TCI is proud to partner with Tsinghua University and its prestigious
faculty to facilitate the development of future design engineers in China",
said Stephen Maneatis, Chief Executive Officer of True Circuits. "Having
access to high-quality IP will enable Tsinghua University students to
achieve real world performance in their research and development activities
and push the boundaries of what is possible. TCI has a long history of
partnering with universities and research institutions around the world, so
supporting Tsinghua University in China will further our passion for
excellence in education and pushing the state-of-the art."
About True Circuits in China
True Circuits PLL and DLL IP has been used in more than 75 products by over
35 Chinese technology companies since 2007. TCI regards China as a key
market for its IP designs and continues to expand market share and product
reach with the help of its China sales representative, Pinnacle Design
About True Circuits PLLs and DLLs
True Circuits offers a complete family of standardized and silicon-proven
general purpose, clock generator, deskew, spread spectrum, IoT and Ultra
PLLs and DDR DLLs that spans nearly all performance points and features
typically requested by ASIC, FPGA and SoC designers. These high quality,
low-jitter PLL and DLL hard macros are suited to a wide variety of interface
standards and chip applications. They are pin-programmable, highly process
tolerant and reusable. They are also easy to integrate and are fully
supported, so customers can reduce both design and silicon risks.
True Circuits PLLs support a wide range of frequencies, multiplication
factors and functions over which they deliver optimal performance, avoiding
the cost and complexity of licensing multiple point-solution PLLs from
foundries or other vendors. TCI's DLLs are available in mutli-slave and
multi-phase versions and different sizes and form factors. They delay a set
of signals by precise and adjustable fractions of a reference clock cycle
independent of voltage and temperature and are ideal for high-speed DDR and
ONFI interface applications. Customized PLL and DLL solutions are also
available for specialized chip applications.
True Circuits PLLs and DLLs are available for immediate customer delivery in
TSMC, GLOBALFOUNDRIES and UMC processes from 180nm to 7nm.
For more information about True Circuits timing IP products, visit
About True Circuits DDR PHYs
The DDR 4/3 PHY is a high-performance, scalable system using a radically new
architecture that continuously and automatically adjusts each pin
individually, correcting skew within byte lanes. This state-of-the-art
tuning acts independently on each pin, data phase and chip select value.
Read data eye and gate timing are also continuously adjusted. Automatic
training is included for multi-cycle read gate timing and write leveling,
write data eye timing, and internal and external (on DRAM) Vref setting.
The PHY employs a localized and optimized PHY-to-memory controller interface
to ease timing closure. The circuitry in each pin is able to measure the
data eye and jitter, and calculate flight delays. The PHY also includes a
full speed read/write BIST, which tests the complete read and write paths of
every pin simultaneously with pseudo-random data.
Remarkable physical flexibility allows the PHY to adapt to each customer's
die floorplan and package constraints, and is delivered and verified as a
single unit for easy timing closure with no assembly required. The PHY is
also DFI 3.1 compliant, and when combined with a suitable DDR 4/3 memory
controller, a complete and fully-automatic DDR 4/3 system is realized.
The True Circuits DDR 4/3 PHY is initially available for customer delivery
in TSMC's 28nm HPC/HPC+ process. The PHY will be available in additional
TSMC processes in the very near future. Interested customers can obtain more
product information on the web at
www.truecircuits.com/ddr_phy.html or by
contacting True Circuits at firstname.lastname@example.org.
About True Circuits
True Circuits develops and markets a broad range of industry leading PLLs,
DLLs and DDR PHY hard macros for ICs for the semiconductor, systems and
electronics industries. TCI's robust state-of-the-art circuits, methodical
and proven design strategy, and close association with the world's leading
foundries, IDMs, and design services companies allow the company to quickly
and reliably create new and innovative designs in a variety of advanced
process technologies. Over the last 19 years, True Circuits has
distinguished itself as the technology leader in the timing IP space, and
its PLLs and DLLs are used extensively around the world in its customers'
products with production volumes in the billions.
True Circuits is headquartered at 4300 El Camino Real, Suite 200, Los Altos,
California 94022 and can be found on the web at
www.truecircuits.com. Product inquiries can
be made by calling the company directly at (650) 949-3400 or via e-mail at
U.S. Press Contact: Kimberly Toan, True Circuits, Inc., (650) 949-3400, Ext.
China Press Contact: Lily Liu, Pinnacle Design Systems, Ltd., +86 137 7445