July 20-24, 2020
True Circuits, Inc. (TCI), a leading provider of analog and mixed-signal intellectual property (IP) for the semiconductor, systems and electronics industries.
What, When and How
At the virtual Design Automation Conference (DAC) from July 20-24, True Circuits will have representatives available to answer questions about our complete line of silicon proven PLLs, DLLs and DDR 4/3 PHYs.
Attendees can visit the TCI virtual booth each day of the conference by clicking on the following link to the DAC website:
Attendees can request in advance a virtual meeting time slot for any day of the conference between 10:30 AM - 1:30 PM PDT. At the appointed meeting time, attendees can enter the virtual meeting using the navigation buttons on the TCI virtual booth webpage.
For more information about True Circuits' PLLs, DLLs and DDR PHYs, please visit www.truecircuits.com.
For more information about the Design Automation Conference, please visit www.dac.com.
About True Circuits PLLs and DLLs
True Circuits offers a complete family of standardized and silicon-proven general purpose, clock generator, deskew, spread spectrum, IoT and Ultra PLLs, and multi-slave and multi-phase DLLs that spans nearly all performance points and features typically requested by ASIC, FPGA and SoC designers. These high quality, low-jitter PLL and DLL hard macros are suited to a wide variety of interface standards and chip applications. They are pin-programmable, highly process tolerant and reusable. They are also easy to integrate and are fully supported, so customers can reduce both design and silicon risks.
True Circuits PLLs support a wide range of frequencies, multiplication factors and functions over which they deliver optimal performance, avoiding the cost and complexity of licensing multiple point-solution PLLs or fiddling with digital PLLs. TCI's PLLs are available with ring-oscillator and LC-tank architectures, fractional-N division and frequency spreading for EMI reduction. TCI's DLLs are available in multi-slave and multi-phase versions and different sizes and form factors. They delay a set of signals by precise and adjustable fractions of a reference clock cycle independent of voltage and temperature and are ideal for high-speed DDR and ONFI interface applications. Customized PLL and DLL solutions are also available for specialized chip applications.
True Circuits PLLs and DLLs are available for immediate customer delivery in TSMC, GLOBALFOUNDRIES and UMC processes from 180nm to 6nm. For more information about True Circuits IP products, visit
About True Circuits DDR PHYs
The DDR 4/3 PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adjusts each pin individually, correcting skew within byte lanes. This state-of-the-art tuning acts independently on each pin, data phase and chip select value. Read gate and data eye timing are also continuously adjusted. Automatic training is included for multi-cycle write leveling and read gate timing, read/write data eye timing, and PHY Vref and DRAM Vref settings.
The PHY employs a localized and optimized PHY-to-memory controller interface to ease timing closure. The circuitry in each pin is able to measure the data eye and jitter, and calculate flight delays. The PHY also includes a full speed read/write BIST, which tests the complete read and write paths of every pin simultaneously with pseudo-random data.
Remarkable physical flexibility allows the PHY to adapt to each customer's die floorplan and package constraints, yet is delivered and verified as a single unit for easy timing closure with no assembly required. The PHY is DFI 4.0 compliant, and when combined with a suitable DDR memory controller, a complete and fully-automatic DDR system is realized.
The True Circuits DDR 4/3 PHY hard macro is silicon proven and immediately available for customer delivery in TSMC's 28nm HPC/HPC+ process. The PHY will be available in additional TSMC and GLOBALFOUNDRIES processes in the very near future. Interested customers can obtain more product information on the web at http://www.truecircuits.com/ddr_phy.html or by contacting True Circuits at email@example.com.
About True Circuits
True Circuits develops and markets a broad range of industry leading PLLs, DLLs and DDR PHY hard macros for ICs for the semiconductor, systems and electronics industries. TCI's robust state-of-the-art circuits, methodical and proven design strategy, and close association with the world's leading foundries, IDMs, and design services companies allow the company to quickly and reliably create new and innovative designs in a variety of advanced process technologies. Over the last 22 years, True Circuits has distinguished itself as the technology leader in the timing IP space, and its PLLs and DLLs are used extensively around the world in its customers' products with production volumes in the billions.
True Circuits is headquartered at 4300 El Camino Real, Suite 200, Los Altos, California 94022 and can be found on the web at www.truecircuits.com. Product inquiries can be made by calling the company directly at (650) 949-3400 or via e-mail at firstname.lastname@example.org.
Press Contact: Kimberly Toan, True Circuits, Inc., (650) 949-3400, Ext. 3404, email@example.com.
Acronyms and definitions
ASIC Application Specific IC
DLL Delay-Locked Loop
DDR Double Data Rate
FPGA Field Programmable Gate Array
IC Integrated Circuit
IoT Internet of Things
IP Intellectual Property
ONFI Open NAND Flash Interface
PLL Phase-Locked Loop
PHY Physical Interface
SoC System on a Chip
The IoT PLL is a trademark of True Circuits, Inc.
The Ultra PLL is a trademark of True Circuits, Inc.
The True Circuits logo is a trademark of True Circuits, Inc.
All other trademarks and tradenames are the property of their respective owners.