July 10-12, 2023, Moscone Convention Center, West Hall, Booth #1335
True Circuits, Inc. (TCI), a leading provider of analog and mixed-signal
intellectual property (IP) for the semiconductor, systems and electronics
At the 60th Design Automation Conference (DAC), TCI will introduce its
powerful JSPICETM simulation and design
environment which has been used by True Circuits over the last 25 years
to create complex analog and digital IP and will now be available to the
public initially through a beta test. TCI will also showcase its complete
line of high performance and general purpose analog and synthesizable
PLL and DLL IP, as well as its innovative and flexible DDR PHY. True
Circuits is also celebrating its 25th year in business!
TCI had its humble beginnings in early 1998, with a small but highly
motivated team working out of a conference room at its initial customer.
The challenge in these early days of the IP industry was to convince big
companies they could confidently license analog timing IP from a small
company. TCI quickly realized that it had to devise a family of standardized
timing IP to cover a variety of chip applications, offer customization
to address existing legacy requirements and focus on quality to make IP
integration and testing seamless. With the goal of supporting many
customers, ever changing interface standards and any foundry/IDM process,
TCI took the dramatic decision to develop many of its own CAD tools to
eventually automate all aspects of the design flow.
With the hard work and dedication of many talented employees over the
last 25 years, TCI has implemented a powerful and highly automated
simulation and design environment called JSPICETM that has allowed us to easily support
many IP design types (PLLs, DLLs, DDR PHYs), all major foundries and
most IDM processes and process variants, and hundreds of semiconductor
customers and design partners from 250nm to 4nm. With a global customer
base covering a wide spectrum of chip applications and many billions of
chips working in the field, True Circuits is immensely proud of what we
have accomplished and the impact we have had on the semiconductor
True Circuits has always measured our success by the success of our
customers. Over the past 25 years, we have had the privilege of working
on the most prevalent consumer electronic products and the challenge of
meeting the toughest requirements, but it has always been the learning
and the relationships we have developed with our customers and partners
that means the most to us. Please stop by our booth to say hi and share
some memories from the years gone by. We would be happy to talk about
the future as well!
In addition to celebrating 25 years of timing excellence, True Circuits
will introduce the JSPICE simulation and design environment to DAC
attendees, and will offer daily presentations and demos highlighting the
features and uses of this powerful design platform. JSPICE has been under
continuous development and use by True Circuits for over 25 years to
create complex analog and digital circuits from 250nm to 4nm. JSPICE
greatly simplifies and expedites the process of designing and characterizing
complex analog and digital circuits by dramatically facilitating and
enhancing the process of running simulations and interpreting their
results. We are glad to discuss how interested users, whether individuals,
students or employees of companies, can join the beta test in advance
of a commercial release and start benefitting from and contributing to
TCI will also showcase its high performance, silicon proven DDR PHY
with fully automatic training managed by a light weight special purpose
processor, and remarkable physical flexibility to adapt to each customer's
die floorplan and package. The PHY supports LPDDR5, DDR4, LPDDR4, DDR3,
and LPDDR3 protocols, and is available in a variety of TSMC processes
from 40nm to 4nm. The availability of this silicon proven PHY means
customers can now license a PHY with significant performance and features
without all the implementation and timing closure hassles that are common
with current DDR offerings. During the show, we will be giving short
presentations and demos of our DDR PHY in action. This will be a great
opportunity to ask questions and learn what makes a TCI DDR PHY hard
macro one special piece of IP.
As always, we are happy to discuss your chip requirements and timing
needs, and recommend the best analog or synthesizable PLL or DLL from
our complete line of high performance and general purpose timing IP.
These high quality, low-jitter PLL and DLL hard and soft macros are
suited to a wide variety of interface standards and chip applications.
They are pin-programmable, highly process tolerant, reusable and available
for delivery in TSMC, GLOBALFOUNDRIES and UMC processes from 180nm to
We have a lot to celebrate and discuss this year, so please stop by
our booth #1335 and spend some time with the timing experts!
When and Where
Moscone Convention Center, West Hall, San Francisco, CA
True Circuits Booth #1335
Monday - Wednesday, July 10-12, 10:00 AM to 6:00 PM
JSPICETM Presentation Schedule
Monday July 10, 11:00 AM, 2:00 PM and 4:00 PM
Tuesday July 11, 11:00 AM, 2:00 PM and 4:00 PM
Wednesday July 12, 11:00 AM, 2:00 PM and 4:00 PM
Please register for a JSPICETM presentation day and time and also become eligible for a prize at
If you would like a private JSPICE demo at DAC, please register at
For more information about True Circuits' PLLs, DLLs, DDR PHYs and JSPICETM, please visit
For more information about the Design Automation Conference, please visit
JSPICE is a powerful simulation and design environment developed and
used by True Circuits over the last 25 years to create complex analog
and digital circuits from 250nm to 4nm. JSPICE greatly simplifies and
expedites the process of designing and characterizing complex analog and
digital circuits by dramatically facilitating and enhancing the process
of running simulations and interpreting their results. It provides
extended input preprocessing, timing analysis, mixed-mode simulation,
generalized waveform analysis, parametric simulation sweeps and optimization,
parallel simulation job control, network process and cloud management,
and data reduction and output processing. Characterization flows allow
users to encapsulate all information needed to automatically and fully
characterize a design and even generate reports. JSPICE also provides a
powerful mechanism for schematic-based electrical checks for use by users
who want all of the advanced features of JSPICE without understanding
any of the details. While JSPICE includes a core SPICE simulator with
some features facilitated by the JSPICE language, it can work with any
SPICE simulator. For more information about JSPICE, visit
About True Circuits Analog PLLs and DLLs
True Circuits offers a complete family of standardized and silicon-proven
general purpose, clock generator, deskew, spread spectrum, IoT and Ultra
PLLs, and multi-slave and multi-phase DLLs that spans nearly all performance
points and features typically requested by ASIC, FPGA and SoC designers.
These high quality, low-jitter PLL and DLL hard macros are suited to a
wide variety of interface standards and chip applications. They are
pin-programmable, highly process tolerant and reusable. They are also
easy to integrate and are fully supported, so customers can reduce both
design and silicon risks.
True Circuits PLLs support a wide range of frequencies, multiplication
factors and functions over which they deliver optimal performance,
avoiding the cost and complexity of licensing multiple point-solution
PLLs or fiddling with digital PLLs. TCI's PLLs are available with
ring-oscillator and LC-tank architectures, fractional-N division and
frequency spreading for EMI reduction. TCI's DLLs are available in
multi-slave and multi-phase versions and different sizes and form factors.
They delay a set of signals by precise and adjustable fractions of a
reference clock cycle independent of voltage and temperature and are
ideal for high-speed DDR and ONFI interface applications. Customized PLL
and DLL solutions are also available for specialized chip applications.
True Circuits PLLs and DLLs are available for immediate customer
delivery in TSMC, GLOBALFOUNDRIES and UMC processes from 180nm to 4nm.
For more information about True Circuits IP products, visit
About True Circuits Synthesizable PLLs and DLLs
The synthesizable Precision PLL generates multiple precision clocks
supporting any modulation scheme from almost DC to 10GHz. The outputs
can be independently dynamically programmed cycle-by-cycle to any clock
period and the clock frequency can be a precise ratio of floating point
numbers times the reference frequency. The integrated phase noise is
better than 500ps RMS. It is ideal for SerDes, processor and DVFS
The synthesizable micro PLL is a small synthesizable general-purpose
PLL that multiplies the reference clock by an integer or fractional-N
value from 1 to 500K. It supports reference clock frequencies as low as
32KHz and output frequencies as high as 3GHz. It can stay locked to the
reference clock while it changes over a 10:1 frequency rang Because it
is synthesizable, it can support spreading as well as other modulation
profiles. It is relatively low power, very fast locking and can quickly
restart from a sleep mode.
The synthesizable micro DLL is a small synthesizable DLL with a master
and multiple slaves topology. It can supp reference frequencies typically
in the range of 500MHz to 3GHz and track reference changes over an 8:1
frequency range while providing 9-bit accuracy in slave delay programming.
Slave delays can be changed glitch free and the DLL can quickly restart
from a sleep mode. It has a very small zero code offset that can be
About True Circuits DDR PHYs
The DDR PHY is a high-performance, scalable system using a radically new
architecture that continuously and automatically adjusts each pin
individually, correcting skew within byte lanes. This state-of-the-art
tuning acts independently on each pin, data phase and chip select value.
Read gate and data eye timing are also continuously adjusted. Fully
automatic training is managed by a light weight special purpose processor
and includes multi-cycle write leveling and read gate training and also
read/write data eye training, including PHY Vref and DRAM Vref settings.
The PHY employs a localized and optimized PHY-to-memory controller
interface to ease timing closure. The circuitry in each pin is able to
measure the data eye and jitter, and calculate flight delays. The PHY
also includes a full speed read/write BIST, which tests the complete
read and write paths of every pin simultaneously with pseudo-random
Remarkable physical flexibility allows the PHY to adapt to each
customer's die floorplan and package constraints, yet is verified and
delivered as a unit for easy timing closure with no assembly required.
The PHY supports LPDDR5, DDR4, LPDDR4, DDR3 and LPDDR3, and is DFI 5.1
compliant. When combined with an appropriate DDR memory controller, a
complete and fully-automatic DDR system is realized.
The True Circuits DDR PHY is silicon proven and immediately available
for customer delivery in TSMC's 28/22nm HPC/HPC+ processes. The PHY is
also available upon request in a variety of TSMC processes from 40nm to
4nm. Interested customers can obtain more product information on the
www.truecircuits.com/ddr_phy.html or by contacting True Circuits at firstname.lastname@example.org.
About True Circuits
True Circuits develops and markets a broad range of industry leading
PLLs, DLLs and DDR PHY hard macros for ICs for the semiconductor, systems
and electronics industries. TCI's robust state-of-the-art circuits,
methodical and proven design strategy, and close association with the
world's leading foundries, IDMs, and design services companies allow the
company to quickly and reliably create new and innovative designs in a
variety of advanced process technologies. Over the last 25 years, True
Circuits has distinguished itself as the technology leader in the timing
IP space, and its PLLs and DLLs are used extensively around the world
in its customers' products with production volumes well into the
True Circuits is headquartered at 4300 El Camino Real, Suite 200, Los
Altos, California 94022 and can be found on the web at www.truecircuits.com.
Product inquiries can be made by calling the company directly at (650)
949-3400 or via e-mail at
Press Contact: Kimberly Toan, True Circuits, Inc., (650) 949-3400,
Acronyms and definitions
ASIC Application Specific IC
DLL Delay-Locked Loop
DDR Double Data Rate
FPGA Field Programmable Gate Array
IC Integrated Circuit
IoT Internet of Things
IP Intellectual Property
ONFI Open NAND Flash Interface
PLL Phase-Locked Loop
SoC System on a Chip
"JSPICE" is a trademark of True Circuits, Inc.
"Precision PLL" is a trademark of True Circuits, Inc.
"micro PLL" is a trademark of True Circuits, Inc.
"micro DLL" is a trademark of True Circuits, Inc.
"IoT PLL" is a trademark of True Circuits, Inc.
"Ultra PLL" is a trademark of True Circuits, Inc.
The True Circuits logo is a trademark of True Circuits, Inc.
All other trademarks and tradenames are the property of their respective owners.