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"We selected TCI's clock generator PLL because of its small size, wide
frequency range and superior low-jitter performance. This will enable our
ASIC customers to successfully implement multiple SPI-4.2 macros in their
high-end telecommunication ASICs and help meet the tight jitter and power
budgets required for 10 Gbps SONET/SDH systems."
Hideya Horikawa Senior Design Engineering Manager Renesas
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The cycle-to-cycle jitter for a divided output clock is the same
percentage of the divided clock period as that for an undivided
clock in the worst case of low-frequency supply/substrate noise.
However, the cycle-to-cycle jitter for any divided clock expressed
in units of time cannot exceed twice the long-term jitter by their
definitions.
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