"We selected TCI's clock generator PLL because of its small size, wide frequency range and superior low-jitter performance. This will enable our ASIC customers to successfully implement multiple SPI-4.2 macros in their high-end telecommunication ASICs and help meet the tight jitter and power budgets required for 10 Gbps SONET/SDH systems."

Hideya Horikawa
Senior Design Engineering Manager
Renesas



The cycle-to-cycle jitter for a divided output clock is the same percentage of the divided clock period as that for an undivided clock in the worst case of low-frequency supply/substrate noise. However, the cycle-to-cycle jitter for any divided clock expressed in units of time cannot exceed twice the long-term jitter by their definitions.


24 Apr 24 TSMC NA Technology Symposium
Santa Clara, California

28 May 24 TSMC China Technology Symposium
Shanghai, China

24-26 Jun 24 Design Automation Conference
San Francisco, California

25 Sep 24 TSMC NA OIP Ecosystem Forum
Santa Clara, California

Copyright © 2002-2024 True Circuits, Inc. All Rights Reserved