"Over the last nine years, ARM has used a variety of high performance PLLs from True Circuits in test and development systems to showcase the performance and flexibility of our flagship processor products. We have now extended the list of processors to include the ARM Cortex-A family of applications processors, including the scalable Cortex-A9 hard core in TSMCıs 40nm G process. TCI's wide range, low-jitter PLLs enable us to demonstrate the speed and functionality of ARM cores and enable our silicon and software partners to optimize and accelerate their own development on advanced Cortex-A platforms."

Peter Hutton
VP Technology & Systems
Processor Division, ARM



When calculating the timing budgets, one may need to consider the worst-case static phase offset, duty cycle error, cycle-to-cycle jitter, and possibly tracking jitter from the PLL, the worst-case skew and jitter from the clock distribution, and the worst-case setup, hold, and clock-to-output times for the clocked elements.


26 Jan 23 TSMC NA Technology Symposium
Santa Clara, California

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Shanghai, China

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Santa Clara, California

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